Computer systems typically include both non-volatile memory, for storing information that has to be retained at power-off, as well as volatile memory.
Dynamic random access memory (DRAM) is a commonly used volatile system memory. It uses an interface with address lines that are typically multiplexed in time. Thus, an address having twice the number of bits as there are address lines is supplied in two successive stages. The most and least significant portions of a complete address are presented sequentially. This arrangement reduces the total number of address lines required. In order to identify which address portion is being sent, each address portion is distinguished by separate control signals. Thus, the DRAM requires control information to access the appropriate memory location.
Synchronous dynamic random access memory (SDRAM) extends this approach by providing a mode in which only the initial address in a sequence of accesses is sent to the memory. Subsequent data locations are read by using additional control signals and a clock signal to indicate when each subsequent data value should be delivered. The SDRAM has internal logic used to advance the data address. In addition to the timing signals, certain control registers of the internal logic of the SDRAM must be loaded with timing control parameters before the sequential access mode may be used.
In addition to the control information needed by the memory itself, the interface logic to the SDRAM also requires initialization. Information is loaded into control registers of the logic subsystem which provides control signals to the SDRAM, to permit access to the SDRAM. Traditionally, this initialization information for the SDRAM memory interface logic and internal logic of the SDRAM memory itself, is provided by instructions read from a separate non-volatile memory in the system.
The disadvantage of these traditional systems is that both the SDRAM and the non-volatile memory in the system have separate interfaces, thus, significantly increasing the number of interface lines and control logic in a system. The present invention seeks to address this problem by creating a non-volatile memory using the same interface as SDRAM thereby providing a system in which both the non-volatile and volatile memories in the system have a common interface. However, using a common: interface, which needs software-controlled initialization, presents a paradox. The instructions for initializing the memory interface logic must be read through the very interface for which the logic has yet to be initialized.